Omar Moataz Mohamed Zawam
Electrical & Computer Systems Engineering Student
📞 +60 11-2124 5515
✉️ omar.moataz520@gmail.com | ozaw0001@student.monash.edu
🌐 omarsserver.tail528e66.ts.net
📍 Sunway City, Malaysia
Highly motivated Electrical and Computer Systems Engineering student at Monash University with a strong technical foundation in embedded systems, digital logic design, and hardware-software co-design. Experience with architecting hardware-level projects, ranging from custom MIPS/RISC-V processors and UART communication modules on FPGAs to analog front-end signal processing and automated industrial PLCs. Skilled in C/C++, Verilog/VHDL, circuit simulation, and EDA toolchains to build reliable low-level hardware solutions.
Education
Monash University
Bachelor of Engineering (Honours) in Electrical and Computer Systems Engineering
Sunway City, Malaysia | Expected Graduation: 2028
Dar Jana International School
American High School Diploma
Jeddah, Saudi Arabia | Graduated: 2023
Technical Skills
Digital & RTL Design
Embedded Systems & Hardware
Hardware Description & Software
Circuit & PCB Design
EDA Tools & FPGA Design
Languages
Projects & Technical Experience
1. Visible Light Communication (VLC) System
Ongoing- Analog Front-End (AFE) Signal Conditioning: Engineered an AFE signal conditioning circuit to amplify and filter high-frequency AC signals captured from a Thorlabs PDA1002 sensor output.
- LTspice Simulation & Fast Switching: Simulated noise-filtering and fast-switching operational amplifier amplification stages in LTspice to interface clean signals with an Intel Agilex 7 FPGA board.
- Hardware Testing & Validation: Executed hands-on hardware testing on breadboard prototypes and performed transient signal analysis in preparation for custom PCB layout design.
1.1 AFE Breadboard Circuit
1.2 Oscilloscope Waveform
1.3 Function Generator Setup
1.4 Circuit Schematic
2. Visible Light Communication (VLC) | BPW-34 Photodiode Receiver
Ongoing- Trans-impedance Amplifier (TIA) Design: Designed and benchmarked an optical receiver stage utilizing a BPW34 PIN photodiode configured with a low-noise trans-impedance op-amp architecture to convert light current into clean voltage waveforms.
- System Modeling & LTspice Analysis: Modeled feedback resistors and parasitic capacitances in LTspice to ensure stable operational dynamic range and fast step-pulse response without ringing.
- Data Acquisition & Microcontroller Integration: Interfaced the photodiode amplification stage with an Arduino Uno microcontroller and digital multimeter setup to verify output voltage swings across varied optical power levels.
2.1 LTspice Schematic
2.2 Photodiode Receiver Circuit
2.3 Arduino Multimeter Test Rig
3. MIPS-Based FPGA Processor Design
Ongoing- 16-Bit Custom MIPS Core: Designed a custom 16-bit MIPS Instruction Set processor core in Verilog targeting the Intel DE10-Lite FPGA using Quartus. Performed RTL synthesis, timing analysis, IP integration, and hardware verification.
- 32-Bit Single Cycle & Pipelined Architecture: Designed a Single Cycle 32-bit MIPS processor with basic ISA; currently expanding the architecture toward a 5-stage pipelined MIPS 32 Release 1 Architecture on a Basys 3 FPGA.
- Core Subsystem Implementation: Constructed core datapath blocks including ALU, internal register files, sign extension modules, multiplexer buses, instruction register (IR), and tick Finite State Machines (FSM).
- Verification & Hardware Simulation: Performed thorough behavioral simulations and waveform analysis in Xilinx Vivado before synthesizing and deployment on FPGA boards.
3.1 Datapath Block Diagram
3.2 ISA Opcode Table
3.3 Vivado Waveform Simulation
3.4 Execution Waveform
4. STM32 Real-Time Audio Sampling & Data Transmission Chain
May 14, 2026- Real-Time ADC Audio Capture: Programmed an STM32 microcontroller using both register-level C and HAL for real-time high-frequency ADC sampling from a ferromagnetic microphone input.
- Digital Signal Processing & Filtering: Configured a second STM32 unit with a real-time moving average filter to process digital audio on the fly and reject outlier ambient noise.
- Python DSP Reconstruction: Authored a host-side Python script to capture live JTAG data streams from the microcontroller and reconstruct them into playable `.wav` audio files.
4.1 STM32 CubeIDE Pinout
4.2 Circuit Schematic
4.3 Dual Board Setup
4.4 Sampling Breadboard
4.5 Voltage Regulator Module
5. Nanosatellite Software & Hardware Development | Occulospace Training
Feb 15, 2026- Space Systems & Firmware Training: Learned about embedded C firmware architecture and long-range telemetry protocols tailored for nanosatellite hardware mockups.
- LoRa Long-Range Telemetry: Integrated a LoRa wireless module to establish low-power, long-range data communication between satellite payload modules and ground telemetry stations.
- Atmospheric Data Acquisition: Interfaced a BMP180 barometric sensor using I2C in C to capture real-time atmospheric pressure and altitude telemetry data.
5.1 Flight Team Hardware
5.2 Flight Mockup Unit
5.3 Team Presentation
6. Automated Industrial Vending System
Oct 5, 2025- PLC Ladder Logic & Pneumatic Control: Developed an automated mechanical vending control system utilizing PLC ladder logic and pneumatic actuators inside Siemens TIA Portal.
- Multi-Sensor Integration: Integrated photoelectric IR sensors for process sequencing and bottle indexing across the mechanical assembly.
- Fault Diagnostics & Hardware Safety: Programmed real-time diagnostic routines to instantly detect hardware faults, liquid leaks, and operational state errors.
6.1 Laboratory Rig Test
6.2 Industrial Vending Rig
6.3 SolidWorks CAD Design
7. Infrared Sensor HC-SR501 with Fading Effect PCB Implementation
Oct 5, 2025- Custom Circuit & Schematic Design: Designed a custom PCB schematic in KiCAD integrating an HC-SR501 PIR motion sensor with a discrete fading LED output driver stage.
- Power Switching & Smooth Fading: Utilized an IRFZ44N N-channel MOSFET driven by an adjustable RC timing circuit to achieve gradual LED brightness dimming and turn-off delays.
- PCB Layout & Routing: Completed component placement, footprint assignment, trace routing, ground plane creation, and DRC optimization for physical production readiness.
7.1 3D PCB Layout Model
7.2 PCB Schematic Diagram
8. UART Transceiver Design & Hardware Implementation
Ongoing- Full-Duplex Protocol Implementation: Designed and implemented a full-duplex Universal Asynchronous Receiver-Transmitter (UART) protocol in Verilog/VHDL for hardware serial communication.
- Custom Baud Rate Generator & FSMs: Engineered a custom Baud Rate Generator and built Finite State Machines (FSMs) for transmitting (TX) and receiving (RX) 8 bit data frames.
- Synthesis & Hardware Verification: Synthesized and verified the digital communication logic on FPGA hardware with custom timing and state transitions.
8.1 UART Architecture Diagram
8.2 FPGA Hardware Board
9. Ubuntu Remote Cloud Server & Custom NAS
Ongoing- Secure Remote Networking: Configured Tailscale and encrypted SSH to establish secure, remote file access for cloud storage.
- Portfolio Hosting & System Management: Managed system configuration and hosted personal portfolio services securely off Linux server infrastructure.